This invention relates to complementary field effect transistors formed by ion implantation, and in particular to a structure and method of fabrication which permit high packing density.
Complementary field effect transistors (hereinafter designated CMOS), which comprise n-channel and p-channel devices formed in the same substrate, are recognized as advantageous in many applications requiring low power dissipation and fast switching speeds. Usually, the devices are formed by diffusion or implantation of a p-type "tub" in an n-type silicon substrate so that the n-channel device is fabricated in the tub and the p-channel device is fabricated in the adjacent portion of the substrate. This procedure necessarily led to the constraint that the concentration at the surface in the tub was much greater than the surface concentration of the substrate. Device constraints followed in terms of capacitance densities, threshold voltages and breakdown voltages.
It has thus been proposed to form the p-channel device in a second tub of n-conductivity type and higher impurity concentration than a more lightly doped substrate adjacent to the p-type tub so that control of the p-channel device could be optimized. These tubs are typically formed by successive surface implantations of boron and phosphorous impurities followed by a heating step whereby the impurity regions are driven into the bulk of the substrate (see, e.g., U.S. Pat. No. 3,821,781, issued to Chang). Using either the single tub or twin tub approach, a considerable amount of semiconductor area is needed due to the fact that the tub impurities will diffuse laterally as well as vertically during the drive-in to establish the desired tub depth. This is particularly troublesome in the twin-tub process since any significant overlap of the two tubs results in decreased doping concentration of each tub at the boundaries which can cause punch through or field inversion channeling during device operation. Typically, the separation of the implantation or diffusion mask windows for source and drain regions must be at least approximately 12 .mu.m to avoid such effects when the tubs are diffused a vertical distance of 6 .mu.m. While such dimensions are adequate for present circuits, it is desirable to save as much space as possible in future generations of IC circuits.
Therefore, it is a primary object of the invention to provide a CMOS structure and method of manufacture which requires little semiconductor space and therefore permits a high packing density.
It is a further object of the invention to define such a structure using a minimum number of masking steps.